The present invention relates to a ferroelectric memory array having a memory cell field composed of a multiplicity of memory cells which each have at least one selection transistor and one storage capacitor and can be driven via word lines and bit lines.
It is known that the nonvolatility of ferroelectric memory arrays is based on a ferroelectric effect in which the polarization of dipoles within an insulator is retained despite the absence of an external electrical field. In other words, the retention of the stored information has the effect that an electrical field cannot be applied to a storage capacitor of the memory array.
However, in integrated circuits, it is not possible to avoid a situation in which small voltage differences occur at the electrodes of ferroelectric storage capacitors particularly due to parasitic components. The components increase or attenuate the polarization of the dielectric depending on the polarization of the dielectric of the storage capacitor and depending on the polarity of the voltage differences.
The voltage differences can also be referred to as interference pulses. The stored information is thus attenuated to a greater or lesser degree depending on the number and/or the amplitude of the interference pulses. In the worst case, incorrect evaluation may even occur during the reading of the memory array, which in practical terms is equivalent to a data loss.
This will be explained in more detail below with reference to a hysteresis curve of a ferroelectric storage capacitor. The hysteresis curve shows that when a voltage V=0 is applied two polarization states which can store information are produced. If the polarization migrates from a first point to a second point due to an interference pulse, for example, and if, after the decaying of the interference pulse, the voltage is 0 again, the polarization does not return to the first point but rather migrates to a third point, which lies below the first point. A plurality of interference pulses can thus ultimately cause the information to be lost.
The coupling of interference pulses while a memory array is operating also depends on the concept that has been applied for the memory array.
In the so-called VDD/2 concept, interference pulses are generated in particular by the capacitive coupling of voltage fluctuations at a common electrode of all the ferroelectric storage capacitors, for example when the memory array is switched on and off, and by a leakage current from disabled PN junctions.
With respect to the pulse concept, capacitive coupling of a pulsed electrode rail onto memory cells that have not been selected is a particular cause of interference pulses.
Furthermore, in the VDD/2 and pulse concept, charge injection and capacitive coupling of the selector transistor or transfer gate give rise to interference pulses.
Finally, in the NAND concept, the voltage drop across the transistors resulting from the current that flows during the reading and writing of a memory cell causes interference pulses.
In the VDD/2 concept there are two approaches to solving the leakage current problem: both are based on the fact that the charge which flows away through the disabled PN junction is replenished either continuously or cyclically by the selector transistor of the memory cell. However, it is possible to switch on the selector transistors continuously only as long as the memory array is not being accessed. However, if the memory array is in fact accessed, just one word line of the memory cell field may be active, while all the other word lines must be switched off. After the memory access, all the word lines must then be switched on again, which gives rise to a large increase in the power requirement due to the high capacitive load. Cyclical switching on of the selector transistors also has the disadvantage that the leakage current gives rise to interference pulses at the storage capacitors between the cycles and these interference pulses can at most be limited in terms of their amplitude. An aggravating factor is that the leakage current of a disabled PN junction is not only subject to severe fluctuations but also rises considerably with the temperature.
In the pulse concept, in order to save chip area and keep the memory array as small as possible, usually twice as many storage capacitors are connected to a common electrode rail than are addressed during a reading or writing access. In order to avoid this, the area of a memory cell would have to be substantially increased, which is, however, not a desirable aim for reasons of costs.
In a NAND-like configuration of the memory cells that can also be used in combination with the VDD/2 concept, the leakage current problem of disabled PN junctions is solved. However, interference pulses occur at the adjacent cells due to the finite resistance of the transistors during the reading or writing of the memory cells.
There is at the moment still no satisfactory solution for the problem of charge injection and capacitive coupling of the selector transistors which occurs in the VDD/2 concept and pulse concept. However, this problem might create fewer difficulties in the future because the channel charge of field-effect transistors is continuing to decrease as the integration density increases.
An existing two-transistor/two-capacitor memory cell (2T2C memory cell) in which information is stored in a complementary fashion, has the advantage that no reference cell is required.
A single-transistor/single-capacitor memory cell (1T1C memory cell) can be used both for an xe2x80x9copenxe2x80x9d bit line configuration and for a xe2x80x9cfoldedxe2x80x9d bit line configuration. In both cases a reference voltage is necessary to evaluate a read signal.
Both the 2T2C memory cell and the 1T1C memory cell are suitable for the VDD/2 concept and for the pulse concept.
In all memory arrays which use such memory cells, the above-mentioned problems owing to interference pulses occur irrespective of which concept the memory array is based on.
It is accordingly an object of the invention to provide a ferroelectric memory array that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which information losses caused by interference pulses are reliably avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a ferroelectric memory array. The ferroelectric memory array has a memory cell field containing a multiplicity of memory cells. Each of the memory cells has at least one selector transistor with a control terminal, a short-circuit transistor with a controllable path and a control terminal, and a storage capacitor with electrodes. The controllable path of the short-circuit transistor is disposed between the electrodes of the storage capacitor. The short-circuit transistor has a different switch-on voltage than the selector transistor. Word lines are connected to and drive the memory cells. More specifically, the word lines are connected to the control terminal of the selector transistor and to the control terminal of the short-circuit transistor. Bit lines are provided and are connected to the memory cells.
In order to achieve this object, a ferroelectric memory array of the type specified at the beginning is characterized according to the invention by a short-circuit transistor which is located above each storage capacitor and short-circuits the electrodes of the storage capacitor.
In order to avoid disadvantageous influences of the interference pulses, an additional transistor is therefore provided for each ferroelectric storage capacitor in the memory array according to the invention, the additional transistor being capable of short-circuiting the electrodes of the ferroelectric storage capacitor. The additional transistor may either be of the same type as the selector transistor, that is to say, for example, a transistor of the enhancement type with a positive switch-on voltage in the case of N-type channel field-effect transistors or else, preferably, a transistor of the depletion type with a negative switch-on voltage in the case of N-type channel field-effect transistors. A transistor of the depletion type is particularly advantageous because it provides an effective protection for the ferroelectric storage capacitor both in the active operating state and in the switched-off state in the form of a Faraday cage.
If the switch-on voltage is carefully chosen, it is also possible to ensure that the memory array does not require any additional area in comparison to a one transistor, one capacitor (1T1C) memory cell.
The storage capacitor can be disposed as a stacked capacitor above the selector transistor or offset as an xe2x80x9coffsetxe2x80x9d, capacitor next to the selector transistor.
A method for operating the ferroelectric memory array is distinguished in that after a reading or writing process both electrodes of the storage capacitor are placed at the same potential by driving by the short-circuit transistor.
In accordance with an added feature of the invention, the selector transistor and the short-circuit transistor are alternately connected to the word lines and the word lines serves as both a word line and a control line.
In accordance with an additional feature of the invention, the short-circuit transistor is a depletion type field-effect transistor.
In accordance with another feature of the invention, the storage capacitor is a stacked capacitor disposed above the selector transistor. Alternatively, the storage capacitor is an offset capacitor disposed next to the selector transistor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a ferroelectric memory array including a memory cell field containing a multiplicity of memory cells having selector transistors with control terminals, short-circuit transistors with controllable paths and control terminals, and storage capacitors with electrodes. Each of the controllable paths of the short-circuit transistors is disposed between respective ones of the electrodes of the storage capacitors. The short-circuit transistors have a different switch-on voltage than the selector transistors. Word lines are connected to and drive the memory cells, the word lines are connected to the control terminals of the selector transistor and to the control terminals of the short-circuit transistors. Bit lines are provided and are connected to the memory cells.
In accordance with a concomitant feature of the invention, the selector transistors and the short-circuit transistors are alternately connected to the word lines and the word lines serving as both a word line and a control line.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a ferroelectric memory array, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.